The present invention generally relates to apparatus and methods for phase and frequency estimation of a time domain signal and, more specifically, to a phase locked loop (PLL)-based apparatus and methods for phase and frequency estimation.
It is well recognized that it is desirable to be able to transmit synchronously digital signals from one node to another in a digital transmission system. However, if the average rate of transmission of bits from a node is not exactly equal to the average rate incoming to the node, errors occur. Such errors are defined as slips. A slip means that bits are arbitrarily deleted if the input transmission rate exceeds the output rate, or that bits are repeated or inserted arbitrarily if the input transmission rate is slower than the output rate. To assure synchronization and avoid slips, the nodes must be synchronized to a common reference signal. To this end, each node includes a local timing signal generator, commonly referred to as a local clock, which generates timing signals at a predetermined frequency. The local clock is adjusted to be in synchronization with a reference signal.
Referring to FIG. 1, there is shown a conventional linear phase locked loop (PLL) 10. In its most fundamental form, a phase detector 12 in the conventional PLL 10 is a four-quadrant multiplier 14. An input signal 16 may be a frequency/phase modulated (co)sinusoidal (shown as cosinusoidal, but could be a sinusoidal waveform as well) waveform, such as A cos [(ωct+φ(t)], wherein A is the amplitude of the waveform, ωct is the phase due to the carrier frequency ωc and φ(t) is the initial phase of the waveform. An output signal, Vdet(t), of the phase detector 12, consists of signals operating on both the sum and the difference of the input and feedback signal phases:Vdet(t)=(½)ABKd{sin [2ωct+φ(t)+Θ(t)]+sin [φ(t)−Θ(t)]},wherein B is the amplitude of an output of a voltage-controlled oscillator (VCO) 22, described below, Kd is a gain constant, and Θ(t) is the feedback initial phase.
A lowpass filter 20 may be used to eliminate the sum and pass the phase difference as a driving voltage for the VCO 22. Due to the negative feedback loop operation, the error signal proportional to the phase difference between the input 16 and a feedback 29 signal, is forced close to zero, i.e.,sin [φ(t)−Θ(t)]≈0therefore ensuring operating in the linear portion of the otherwise nonlinear (sine) transfer characteristic of the phase detector 12 when the loop is in lock, i.e., when the output phase Θ(t) tracks the input phase φ(t). The VCO 22 generates an output/reference signal 26, B cos [ωct+Θ(t)], which is used to close the loop 10. Since the VCO output signal 26 is expressed in terms of frequency in rad/sec, an integration is assumed to follow the VCO with an integrator 28. The integrator 28 supplies the phase detector 12 with phase information. Therefore, both of the inputs of the phase detector 12, the input signal 16 and the output 29 of the integrator 28 contain phase information.
As a byproduct of the PLL action, a voltage signal 30 proportional to the change in frequency/phase of the input signal 16 is generated at the lowpass filter output 24 and this voltage represents the system's actual output voltage signal 30, Vlpf(t). Thus, for the input signal, which is frequency- or phase-modulated, this voltage signal 30 becomes the demodulated output of the PLL.
A typical conventional PLL, as shown above, uses a four-quadrant multiplier, e.g., multiplier 14, which results in multiple, complex sums, e.g., between the input signal 16 and the integrator output signal 29, requiring substantial computer processor resources to affect these sums.
As can be seen, there is a need for a simple phase/frequency estimation apparatus and method which may use a simpler, less processor intensive means for obtaining this estimation.